Reverse engineering a chip from its layout: my first ASIC

The figures from the writeup, one per screen, in order.

6 visuals arrow keys or j and k move between them

The warmup chip’s GDS in 3D. Standard cells along the bottom, metal wiring stacked above them, wide power straps on top. The puzzle chip is the same thing with a lot more cells.

2 / 6 in the writeup: Placement is evidence

Scatter of the warmup DEF placement, coloured by instance

3 / 6 in the writeup: Picking an approach

The annotated die image from the puzzle, with the output generator box

4 / 6 in the writeup: Polygons back into wires

Left, the warmup’s given netlist. Right, the same cells pulled out of the polygons with identical wiring. The script does this for the whole chip.

5 / 6 in the writeup: The waveform had the answer’s shape all along

The example VCD in Surfer: two enable windows with input bits on I, a reset pulse between them, a burst on O after each window, success flat

Two enable windows, each with a stream of bits on I. A rst_n pulse between them. A short burst on O after each window. success never moves. The cursor sits on one character of the first burst, 0x47, which is a G.

6 / 6 in the writeup: Letting Z3 find the key

Top: the chip unrolled in time, one copy of the gates per clock cycle, the flip-flops carried between copies. Bottom: how Z3 works through the formula.